IMEKO Event Proceedings

Page 6 of 792 Results 51 - 60 of 7918

Jerzy Nabielec
A “BLIND” CORRECTION OF DYNAMIC ERROR OF A NONSTATIONARY FIRST ORDER TRANSDUCER FOR THE PERIODIC CASE – SIMULATION INVESTIGATION

The paper presents an extension of the “blind correction” method with respect to nonstationary transducers of the first order. An analytical description of the measuring channels’ dynamics is presented for the case where both: the measured signal and the measuring channels’ parameters are varying with same fundamental frequency. The influence of the measuring system parameters on the correction accuracy was investigated using the simulation methods.

Mustafa Keskin, Un-Ku Moon, Gabor C. Temes
A 0.9-V 10.7-MHz 3.6-mW Bandpass ∆Σ Modulator Using Unity-Gain-Reset Opamps

A low-voltage and low-power bandpass ∆Σ modulator is described. In this design, two novel ideas are incorporated: unity-gain-reset and integrating-two-path techniques. A test chip, realized in a 0.35- µ m CMOS process and clocked at both 20 and 40 MHz, provided a dynamic range DR = 45 dB and a signal-to-noise+distortion-ratio SNDR = 36 dB for a 100-kHz signal bandwidth at 5MHz center frequency, and DR = 30 dB and SNDR = 32 dB for a 200-kHz BW at 10MHz center frequency. The supply voltage was 0.8 V for 20 MHz clock, and 0.9 V for 40 MHz clock.

Salim Alahdab, Reza Lotfi, Wouter A. Serdijn
A 1-V 416-nW FULLY INTEGRATED SENSOR INTERFACE IC FOR PACEMAKERS

An ultra-low-power, low-noise sensor interface IC for pacemakers is presented. The proposed architecture is designed to achieve small chip area and a good trade-off between power consumption and noise figure by using current-mode operation. The IECG signal, from 50 mHz-100 Hz, is first filtered by a bandpass filter. Subsequently, the signal output of the filter is converted into a current by a nonlinear transconductance (Gm) cell. The output of the Gm-cell is digitized by a nonlinear 8-bit 1 kS/s Current-mode Successive Approximation ADC to compensate for the nonlinearity of the Gm-cell. The simulated input-referred noise is 5.48 µVrms, achieving a Noise Efficiency Factor of 3.3, and the simulated power consumption for the overall system is 416 nW while operating from a 1 V supply.

S. Marabelli, A. Fornasari, P. Malcovati, F. Maloberti
A 14-BIT BANDPASS MASH SIGMA-DELTA PIPELINE A/D CONVERTER

In this paper a two stage bandpass MASH (multi-stage noise shaping) sigma-delta (Σ∆) modulator is presented. A resolution of 14 bits has been achieved over a 5 MHz band around an intermediate frequency (IF) of 20 MHz with a clock frequency of 80 MHz. This performance is obtained using a 6-th order bandpass Σ∆ modulator followed by a 10 bit pipeline converter. The proposed circuit has been extensively simulated, both at behavioral and at circuit level, and results are illustrated.

Henrik Volkers, Thomas Bruns
A 2-DOF MODEL FOR BACK-TO-BACK SHOCK TRANSDUCER

By applying a two-degree-of-freedom system model (2-DOF) for an Endevco type 2270 back-to-back reference accelerometer, systematic deviations between measured and fitted 1-DOF transfer functions could be improved. Some key information for the identification of the model parameters is found in the frequency range beyond the first resonance, a range which was rarely considered in the past.

Fabio Leccese, Michael Magnone
A 3 BITS DISCRETE PURE LINEAR ANALOG PREPROCESSING FOLDING ADC ARCHITECTURE BASED ON CASCADE CONTROLLED CHANNELS

A very simple circuit for a 3-bits discrete pure linear analog preprocessing folding ADC is presented. The device is based on the folding idea: the DAC, the summing node and the amplifier, fundamental elements of the classical architecture, are eliminated and replaced with an analogical signal preprocessing parallel structure named "channels". All channels are connected as a cascade and only three transistors constitute each one. The circuit has been widely analyzed by simulation and its simplicity guarantees easiness of realization, reduction of power consumption and reduction of total conversion time, making it close to the ADC flash. A first discrete circuit it has been realized and tested.

Di Angelo L., Di Stefano P., Guardiani E., Morabito A.E.
A 3D information framework for automated archaeological pottery archival

The classification of ceramic archaeological fragments is based on shape, dimensions, decorations, technological elements, color and material. Nowadays, all of these features are still recognized and analyzed by a skilled operator. It follows that the resulting characterization of shape and sizes of archaeological fragments is poorly reproducible and repeatable. With a view to overcome these limitations, a computer-based methodology, able to extract automatically several quantitative information from high-density discrete geometric models acquired by the laser scanning of archaeological fragments, was proposed. In this paper, the set of quantitative information obtainable is furtherly broadened, by including the segmentation of some types of morphological features, the identification of the fragment shape type, the evaluation of the longitudinal profile and the estimation of a larger set of dimensional features. Finally, a new 3D information framework is proposed to store the large variety of quantitative information extracted.

Matteo Parenti, Andrea Boni, Davide Vescovi
A 6-b 1Gsample/s SiGe BiCMOS A/D Converter

The paper describes the design of a 1GS/s 6-bit ADC in SiGe BiCMOS technology. Several techniques such as subranging, interpolation and averaging were implemented on the original flash architecture in order to achieve low power consumption without sacrificing linearity and dynamic performance.

Bruno Da Silva, Stephane Bosse, Severin Barth, Steve Torchinsky
A 6-bit 3GS/s FLASH ADC IN BIPOLAR 0.25 µm FOR THE RADIOTELESCOPE SKA

A flash Analog to Digital Converter (ADC) at 3 Giga samples per second (GS/s) was developed using QUBIC4X which is a 0.25 µm SiGeC process from NXP Semiconductors. The ADC has a bandwidth close to 1.2 GHz with a resolution of 6-bit. The full design employs a differential structure. The ADC uses a parallel architecture consisting of the following components: track and hold, comparators, and a fat tree encoder. An embedded test system will help us to validate the data transmission, and it is made by a Linear Feedback Shift Register (LFSR). An additive scrambler block allowed us to transmit the data without an accompanying clock signal. The core of the digital circuit is in Emitter-Coupled Logic (ECL). The input is adapted to 100 Ω differential, and the outputs use standard Low Voltage Differential Signaling (LVDS). The input voltage range is about 0.5 Volts. The complete system has a power consumption of 2.6 Watts and the Effective Number of Bits (ENOB) is higher than 4.4 at 1490 MHz.

Li Wansheng, Li Qingzhong, Zhao Yucheng, Sun Yunhai, Wang Jianguo
A 60 MN Build-Up Force Transfer System

The paper described principle, construction and main specifications of a 60 MN force transfer system (FTS), which is used to transfer or calibrate large force over 20 MN, and to do inter-comparison of force standards. The paper has raised additional budget of its connecting to uncertainty of the force measured by the FTS, and non-uniformity of force applied on the FTS.

Page 6 of 792 Results 51 - 60 of 7918