G. Bernardinis, A. Centuori, U. Gatti, P. Malcovati, F. Maloberti
BAND-PASS SIGMA-DELTA MODULATOR WITH 5 MHZ BANDWIDTH AND 80 MHz IF

In this paper we present a sigma-delta modulator for wide-band base transceiver station receivers. The modulator, based on a four-path architecture, achieves an equivalent sampling frequency of 320 MHz, although the building blocks operate at only 80 MHz. The circuit in simulation achieves 94 dB signal-to-noise ratio with a signal bandwidth of 5 MHz centered around an intermediate frequency of 80 MHz. Behavioral simulations of the complete sigma-delta modulator, including the most important non-idealities, as well as transistor-level simulations of the most critical building blocks are reported.

P. Arpaia, P. Daponte, S. Rapuano
A STATE OF THE ART ON ADC MODELING

The state of the art of the research on modelling of analog-to-digital converter-based measuring devices is surveyed. Main topics of modelling are reviewed according to the fields of prevailing scientific interest in metrological research such as quantization models, error models, and correction-aimed models. In these fields, recent developments are analysed with the aim of focusing both the contemporary situation and the imminent trends.

Voicu Groza, Boris Dzerdz
FPGA BASED IMPLEMENTATION OF A PREDICTIVE FLOATING-POINT ANALOG-TO-DIGITAL CONVERTER

Floating Point Analog-to-Digital Converters (FP-ADC’s) were developed and used to quantize large dynamic range signals in applications where large signals need not be encoded with a precision greater than that required for small signals. Comparing floating-point with uniform quantization, it was shown that FP-ADC requires much smaller silicon area for the same dynamic range, but at the cost of doubling the conversion time.
To improve the resolution and speed of conversion of such an FP-ADC, a higher precision predictive floatingpoint architecture was conceived (PFP-ADC). The PFPADC consists of two parallel uniform A/D converters, a D/A converter, a fixed-gain amplifier and a subtraction circuit. The current subtrahend of the subtraction circuit is based on the previous sample acquisition, while the current minuend is the measured signal itself. Determination of mantissa and exponent occurs in parallel.
This paper presents the principle used to improve the resolution of FP-ADC quantized signals, and its proofof- concept FPGA based implementation. The resulting improved SNR that was achieved by using the proposed FP-ADC is better than that of other FP-ADCs, while the conversion time is shorter due to the use of prediction techniques and statistical characteristics of the measured signals.

Henrik Lundin, Mikael Skoglund, Peter Händel
A FRAMEWORK FOR EXTERNAL DYNAMIC COMPENSATION OF AD CONVERTERS

External correction of analog-to-digital converters is considered. First, a dynamic correction scheme is proposed to comprise bit-masking. Next, a framework for analyzing the effects of bit-reduced table indexing is derived. This framework is finally applied in an optimization problem for bit allocation in the bit mask of the introduced correction scheme.
Both the dynamic correction method and the optimization problem are exemplified with experimental AD data. The results indicate that the considered correction scheme is superior to static schemes, and that the choice of bit mask is crucial, motivating the analysis framework.

Vladimir Haasz, Jaroslav Roztocil , Dominique Dallet, David Slepicka
COMPARISON OF PARAMETERS OF SYSTEMS USED FOR AD CONVERTERS AND MODULES TESTING

The paper presents results of ADC testing systems comparison between Laboratoire de microélectronique IXL, University Bordeaux and ADCM&T Laboratory, Dept. of Measurement of FEE CTU, Prague. The comparison was performed using transportable reference AD device designed and developed in FEE CTU.