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Olli Vainio
ADAPTIVE SCHEME FOR OVERSAMPLED FRONT ENDS

A computationally efficient adaptive filtering scheme for oversampled A/D converters is discussed. The decimating digital filter is constructed as a combination of a sinc decimator and an adaptive predictor. A reduced-rank adaptive algorithm with two adaptive parameters is proposed for this purpose avoiding the complexity of the commonly used full-rank algorithms. The characteristics of the adaptive filter are considered, and a comparative example of data signal processing is shown.

G.C. Cardarilli, A. Del Re, R. Lojacono, A. Nannarelli, M. Re
PERFORMANCE COMPARISON BETWEEN TRADITIONAL AND RNS-BASED ADC

Recently a new architecture for an analog to Residue Number System converter was proposed by the authors. In this paper a comparison of the performances, in terms of probability of LSB error due to internal noise, between a traditional ADC converter and this said analog to RNS converter is given.

Reinhard Kindt, Richard Ižák
AN ANALOG APPROACH TO COMPENSATE FOR OpAmp OFFSET AND FINITE GAIN IN SC CIRCUITRY: A CASE STUDY OF A CYCLIC RSD ADC

Design of high-resolution Nyquist rate A/D converter necessitates the usage of advanced circuit techniques to compensate for arising analog errors. In switched capacitor ADC, besides the well know techniques such as bottom plate sampling, mismatch-independent and redundant (RSD: 1.5 bit/stage) conversion for the elimination of charge injection, capacitor mismatch, comparator and offset sensitivity, respectively, the most utilised circuit techniques are those for OpAmp’s offset and finite gain errors cancellation. An alternative technique for compensation of the errors due to finite gain and offset of Opamp in SC circuits is proposed. This novel method features a charge addition and is compared to so far used approaches based on voltage addition. The concept and the results of a 5 V CMOS implementation of cyclic RSD ADC with ratio-independent SC technique using this correction method are discussed.

Alberto Die, Maurizio Valle
EVALUATION OF TIME RESOLUTION OF NMOS SAMPLING SWITCHES

Usually in CMOS line receivers and downconversion mixers, a key component is the NMOS sampling switch. When designing sampling switches, one has usually to trade off resolution against bandwidth and aperture time. In this perspective, we modeled the aperture time of the NMOS sampling switch for low swing voltage signals taking also into account the dependence of the threshold voltage on the body effect. Then we compared the aperture time behaviour using three submicron CMOS technologies (0.8, 0.5 and 0.25 μm minimum channel length respectively). The results indicate that an aperture time of about 100 ps is achievable with a CMOS 0.25 μm minimum channel length technology working at low supply voltage.

I. Vecera, R. Vrba
NOVEL PIPELINED SWITCHED-CURRENT A/D CONVERTER FOR SMART SENSORS

This paper describes pipelined switched-current A/D converter designed in 0.6 µm BiCMOS technology. Modified conventional-restoring algorithm, called redundant-sign-digit (RSD), was implemented what decreases the amount of high-precision components. Two modes of operation are possible. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Proposed A/D converter is suitable for conversion of the current with very low amplitude from analog into digital domain. Current mode enables operation down to 3 V thus is suitable for battery powered applications. The system integrates band-gap reference and independent supervisory circuit with 1% accuracy. Current consumption in sleep mode is less than 1 mA. A/D converter is prepared to meet 1452.2 specifications.

Mark Vesterbacka, K. Ola Andersson, Niklas U. Andersson, J. Jacob Wikner
USING DIFFERENT WEIGHTS IN DACs

In this paper we discuss some properties of different codes with their respective sets of weights to be used in digital-to-analog converters (DACs). The thermometer (unratioed) code is widely used instead of a binary code in the most significant bits of a segmented DAC to reduce errors due to weight and timing mismatch. The binary and thermometer codes are two extremes, where the first offers a small digital hardware cost and the latter a large cost. We have investigated some of the properties of these codes and codes with properties in-between; such as linear, polynomial, and segmented codes. Some new ideas and results on using different sets of weights and how to generate them are presented. We present simulation results for some low-order polynomial codes.

K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, J. Jacob Wikner
COMBINING DACS FOR IMPROVED PERFORMANCE

This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.

R.K. Kamat, G.M. Naik
ANALOGUE TO DIGITAL CONVERTER WITH NON-LINEAR TRANSFER FUNCTION FOR THERMISTOR APPLICATIONS

There exists a disproportionate difference between dynamic range, resolution, and accuracy when the output of sensors having nonlinear characteristics like thermistors are digitized with the conventional linear ADCs. There are several methods to linearise the thermistor characteristics but at the expense of hardware, memory and time efficiency. This paper presents a new simple method of shaping the transfer function of a pulse width modulation ADC as per the thermistor characteristics. It is based on the principle of varying the amplitude of the reference voltage to reach the temperature equivalence of voltage being digitized.

A. Moschitta, D. Petri
EFFECTS OF ADC INTEGRAL NON-LINEARITY ON DIGITAL TRANSMISSION

This paper investigates the effects of Integral Non-Linearity (INL) on the performances of both A/D converters and Digital Communication Systems, which exploit Direct Digital Modulation. The performances of both PCM and Sigma-Delta converters affected by INL are considered and compared. Then, the effects of INL upon the BER performances of an OFDM system are evaluated and modeled. The accuracy of the theoretical model is discussed with respect to the ADC resolution and INL levels. It is shown that a multibit Sigma-Delta converter, operating at a low oversampling ratio, may outperform PCM converters.

D. Macii, P. Carbone, D. Petri
STABILITY ANALYSIS OF OSCILLATORS BASED ON A DELTA–SIGMA TOPOLOGY

The growing demand of mixed–signal integrated circuits encourages the research of Built-In Self-Test (BIST) techniques to achieve simpler and less expensive testing processes. High quality sinusoidal oscillators based on a Δ-Σ topology are an effective solution to perform the test of this kind of devices. Unfortunately, due to the in–loop 1–bit quantizer nonlinearity, several problems of stability have been observed. A stability analysis on the behavior of the oscillator based on a second order Δ-Σ modulator presented in [1] is described in this paper. In particular, it is shown that the oscillator is intrinsically unstable and its complete dynamics is very difficult to predict exactly. Finally, a possible stabilization strategy is proposed.

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