FPGA BASED IMPLEMENTATION OF A PREDICTIVE FLOATING-POINT ANALOG-TO-DIGITAL CONVERTER |
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| Voicu Groza, Boris Dzerdz |
- Abstract:
- Floating Point Analog-to-Digital Converters (FP-ADC’s) were developed and used to quantize large dynamic range signals in applications where large signals need not be encoded with a precision greater than that required for small signals. Comparing floating-point with uniform quantization, it was shown that FP-ADC requires much smaller silicon area for the same dynamic range, but at the cost of doubling the conversion time.
To improve the resolution and speed of conversion of such an FP-ADC, a higher precision predictive floatingpoint architecture was conceived (PFP-ADC). The PFPADC consists of two parallel uniform A/D converters, a D/A converter, a fixed-gain amplifier and a subtraction circuit. The current subtrahend of the subtraction circuit is based on the previous sample acquisition, while the current minuend is the measured signal itself. Determination of mantissa and exponent occurs in parallel.
This paper presents the principle used to improve the resolution of FP-ADC quantized signals, and its proofof- concept FPGA based implementation. The resulting improved SNR that was achieved by using the proposed FP-ADC is better than that of other FP-ADCs, while the conversion time is shorter due to the use of prediction techniques and statistical characteristics of the measured signals. - Keywords:
- quantization, floating point arithmetic
- Download:
- IMEKO-TC4-2002-012.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Conference and Workshop 2002
- Title:
- 4th International Conference on Advanced A/D and D/A Conversion Techniques and their Applications (together with 7th IMEKO TC4 Workshop on ADC Modelling and Testing)
- Place:
- Prague, CZECH REPUBLIC
- Time:
- 26 June 2002 - 28 June 2002