A 0.9-V 10.7-MHz 3.6-mW Bandpass ∆Σ Modulator Using Unity-Gain-Reset Opamps

• Abstract:

  A low-voltage and low-power bandpass ∆Σ modulator is described. In this design, two novel ideas are incorporated: unity-gain-reset and integrating-two-path techniques. A test chip, realized in a 0.35- µ m CMOS process and clocked at both 20 and 40 MHz, provided a dynamic range DR = 45 dB and a signal-to-noise+distortion-ratio SNDR = 36 dB for a 100-kHz signal bandwidth at 5MHz center frequency, and DR = 30 dB and SNDR = 32 dB for a 200-kHz BW at 10MHz center frequency. The supply voltage was 0.8 V for 20 MHz clock, and 0.9 V for 40 MHz clock.
• Download:

  IMEKO-IWADC-2003-16.pdf
• DOI:

  _unreg_iwadc-2003.16

Event details:

• IMEKO TC:

  TC4
• Event name:

  IWADC 2003
• Title:

  VIIIth IMEKO TC4 Workshop on ADC modelling and testing

• Place:

  Perugia, ITALY
• Time:

  8 September 2003 - 10 September 2003