IMEKO Event Proceedings

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Franco Maloberti
HIGH-SPEED HIGH-RESOLUTION DATA CONVERTERS FOR BASE STATIONS: TECHNOLOGIES, ARCHITECTURES AND CIRCUIT DESIGN
This paper presents a possible evolution of base station architectures in the frame of the future global communication scenario. Moving from such a view the paper considers the technology trend and its influence on highspeed data converter design. Then, architectures of highspeed, high-resolution converters are resumed. Finally, design techniques and strategies for achieving the requirements of base-station systems are discussed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

António Cruz Serra
NEW TRENDS IN ANALOG TO DIGITAL CONVERTERS TESTING
In this paper, new state of the art analog-to-digital converters (ADCs) testing techniques both static and dynamic are revised and discussed.
Regarding the static test it is shown that a new technique based on the use of small triangular waves superimposed with a variable offset value as input signal, reduces dramatically the test duration. This histogram based technique can be implemented by using low cost generators even for high resolution ADC testing.
In relation to the dynamic test, a variant of the traditional histogram test using Gaussian noise as stimulus signal is discussed. It allows the test of high frequency, or high resolution ADCs in those cases where the traditional sinusoidal stimuli are not available with the required spectral purity. New techniques to grant convergence of the traditional four-parameter sine fitting algorithms traditionally used in time domain tests are also revised.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

R A Belcher, C Asteriou, C J Bury, A Edwards, R Hall, G Lancelin, M Penny
A DSP BASED TEST SYSTEM FOR 'NOISE-SEPARATION' MEASUREMENTS ON ADC AND DAC SYSTEMS
This paper describes the design and application of a 'noise-separation' test system that uses in-system programmable logic devices and a digital signal processor. This offers a low cost approach to multi-tone testing of the wide-bandwidth linearity of both ADC and DAC systems. As the test signal bandwidth is software configurable and uses 1 bit D-A converters it can be applied to a much wider range of applications than more conventional multi-tone test methods. Time-domain processing is expected to provide meaningful results for routine tests in a much shorter time than with FFT analysis.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Y. C. Jenq, Qiong Li
DIFFERENTIAL NON-LINEARITY, INTEGRAL NON-LINEARITY, AND SIGNAL TO NOISE RATIO OF AN ANALOG TO DIGITAL CONVERTER
The Analog to digital converter (ADC) has been widely used in all kinds of modern electronic instruments, so it is desirable to find out the relationship between various errors and the performance of ADC and improve the performance with a low cost operation. This paper studies and tries to quantify the relationship between the differential non-linearity (DNL) error, the integral non-linearity (INL) error and the signal to noise ratio (SNR) performance of an ADC, and investigates various methods to reduce the effect of these errors to increase the SNR. Major results are obtained by computer simulation, while a simple analytic model is also investigated. It is found that the loss of SNR due to DNL roughly follows the “6 dB per LSB” rule, and the major cause of the significant SNR loss is primarily due to harmonic distortion introduced by the INL. The investigation of the analytic model of the INL shows that it can predict the SNR loss very similar to the result obtained by computer simulation. We also study various methods to improve the SNR performance of the ADC. It is found that the Midpoint method, although simple, can almost completely eliminate the effect of the INL. It is also shown that if the ratio of the sampling frequency to the input signal frequency is large, the DNL can be further reduced to improve the SNR by Grouping and Sorting method.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

M. Fonseca da Silva, A. Cruz Serra
A NEW ROBUST FOUR PARAMETER SINE FITTING PROCEDURE
In this paper a new procedure to perform four parameters sine fitting is presented in a closed form, ready for standardization. This new procedure grants convergence of the algorithm, even in those cases where the traditional techniques tend to converge to local minimums of the error function.
This new procedure can also be used to compute the initial values for the traditional four parameters sine fitting algorithm if very high accuracy is required. In such case convergence of the traditional algorithm is also assured.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Jan Holub, Josef Vedral, Miroslav Kubín
IMPROVEMENT OF STEP-GAUSS ADC STOCHASTIC TEST METHOD
Improvement of Analog-to-Digital Converters testing method that is suitable for testing of high-resolution AD converters (e.g. Σ-Δ or dither-based) or on the contrary ultra high-speed AD converters is presented. The method is based on the histogram test driven by stochastic signal with defined probability density function. By repeating of the test for different settings of band-pass filter that is inserted to the input testing signal path it is possible to obtain an estimation of frequency dependency of effective number of bits. The results have to be recalculated to equivalent band-pass filtering. Practical demonstration confirmed wider applicability than for direct band-pass filter application.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

E. Nunzi, P. Carbone, D. Petri
ESTIMATION OF DELTA–SIGMA CONVERTER SPECTRUM
Effects of the windowing process, widely investigated by the scientific literature for narrow–band components embedded in white noise, is not sufficiently detailed when signals are corrupted by colored noise. Such a phenomenon can heavily affect the spectral parameters estimation of the noisy signal. In this paper effects of the windowing on the output of analog–to–digital converters with ΔΣ topology, which present a spectrally shaped quantization noise, is analyzed. In particular, the spectral leakage of both narrow– and wide– band components is investigated and a criterion for choosing the most appropriate window for any given modulator resolution is given. The proposed analysis validates the use of the Hanning sequence as the optimum two term cosine window to be employed for characterizing low order ΔΣ modulators.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Vladimir Haasz, Jaroslav Roztocil , Dominique Dallet, David Slepicka
COMPARISON OF PARAMETERS OF SYSTEMS USED FOR AD CONVERTERS AND MODULES TESTING
The paper presents results of ADC testing systems comparison between Laboratoire de microélectronique IXL, University Bordeaux and ADCM&T Laboratory, Dept. of Measurement of FEE CTU, Prague. The comparison was performed using transportable reference AD device designed and developed in FEE CTU.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Jan Holub, Olli Aumala
DATA PROCESSING AND DITHER ENHANCEMENT OF ADC PARAMETERS – TRENDS, APPLICATIONS, LIMITS
There is no noise-free place on Earth. Most of noisy effects are undesirable and unwelcome, especially in measuring technology. However, there are some measuring methods and algorithms using noise for quality enhancement. These processes are usually called dithering. Basic ideas of these methods were partially assumed from audio and video signal processing many years ago. The field of dithering technologies in measurement became large in recent years.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Henrik Lundin, Mikael Skoglund, Peter Händel
A FRAMEWORK FOR EXTERNAL DYNAMIC COMPENSATION OF AD CONVERTERS
External correction of analog-to-digital converters is considered. First, a dynamic correction scheme is proposed to comprise bit-masking. Next, a framework for analyzing the effects of bit-reduced table indexing is derived. This framework is finally applied in an optimization problem for bit allocation in the bit mask of the introduced correction scheme.
Both the dynamic correction method and the optimization problem are exemplified with experimental AD data. The results indicate that the considered correction scheme is superior to static schemes, and that the choice of bit mask is crucial, motivating the analysis framework.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Anna Domańska
THE EQUALITY OF QUANTIZATION WITH DITHER SIGNAL AND OVERSAMPLING FROM THE POINT OF VIEW OF THE CRITERION OF SNR
SNR is a characteristic of analog-to-digital (A/D) conversion. One of its applications is the valuation of the “effect” of the change of the resolution of A/D conversion. SNR may be improved by modifying the process of discretization in terms of time (sampling) and value (quantization).
The present article discusses the equality of these two types of modification from the point of view of the criterion of SNR.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Voicu Groza, Boris Dzerdz
FPGA BASED IMPLEMENTATION OF A PREDICTIVE FLOATING-POINT ANALOG-TO-DIGITAL CONVERTER
Floating Point Analog-to-Digital Converters (FP-ADC’s) were developed and used to quantize large dynamic range signals in applications where large signals need not be encoded with a precision greater than that required for small signals. Comparing floating-point with uniform quantization, it was shown that FP-ADC requires much smaller silicon area for the same dynamic range, but at the cost of doubling the conversion time.
To improve the resolution and speed of conversion of such an FP-ADC, a higher precision predictive floatingpoint architecture was conceived (PFP-ADC). The PFPADC consists of two parallel uniform A/D converters, a D/A converter, a fixed-gain amplifier and a subtraction circuit. The current subtrahend of the subtraction circuit is based on the previous sample acquisition, while the current minuend is the measured signal itself. Determination of mantissa and exponent occurs in parallel.
This paper presents the principle used to improve the resolution of FP-ADC quantized signals, and its proofof- concept FPGA based implementation. The resulting improved SNR that was achieved by using the proposed FP-ADC is better than that of other FP-ADCs, while the conversion time is shorter due to the use of prediction techniques and statistical characteristics of the measured signals.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

P. Daponte, R. Holcer, L. Horniak, L. Michaeli, S. Rapuano
USING AN INTERPOLATION METHOD FOR NOISE SHAPING IN A/D CONVERTERS
Digital post processing of output data is often used to enhance the ADC Effective Number Of Bits (ENOB). In particular, it can be used to partially recover ENOB restrictions caused by nonlinearities. The paper deals with advantages and disadvantages coming from the application of a proposed nonlinearity correction method based on the Bayes theorem. It allows the reduction of large scale errors in output signal by means of the use of dithering with low peakpeak voltage instead of a high amplitude one. The paper gives a brief description of the method. Then, the results of an experimental investigation carried out on actual ADC output data are presented and discussed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

P. Arpaia, P. Daponte, S. Rapuano
A STATE OF THE ART ON ADC MODELING
The state of the art of the research on modelling of analog-to-digital converter-based measuring devices is surveyed. Main topics of modelling are reviewed according to the fields of prevailing scientific interest in metrological research such as quantization models, error models, and correction-aimed models. In these fields, recent developments are analysed with the aim of focusing both the contemporary situation and the imminent trends.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

G. Pasini, P. A. Traverso, D. Mirri, F. Filicori
TIME-DOMAIN EXPERIMENTAL CHARACTERIZATION OF NONLINEAR DYNAMIC EFFECTS IN S/H-ADC DEVICES
The input/output relationship of a Sample/Hold and Analogue-to-Digital Conversion device (S/H-ADC) can be described as the response of a non-linear system with memory. A general-purpose “black-box” behavioural approach, based on a modified Volterra representation, has been proposed by authors for the modelling of a wide class of non-linear dynamic systems and specifically applied to the characterization of S/H-ADCs. In this paper, the instrumentation set-up and the experimental procedure for the extraction of S/H-ADC model parameters are presented and a novel standard for the characterization of non-linear dynamic effects in this family of measurement systems is proposed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

G. Bernardinis, A. Centuori, U. Gatti, P. Malcovati, F. Maloberti
BAND-PASS SIGMA-DELTA MODULATOR WITH 5 MHZ BANDWIDTH AND 80 MHz IF
In this paper we present a sigma-delta modulator for wide-band base transceiver station receivers. The modulator, based on a four-path architecture, achieves an equivalent sampling frequency of 320 MHz, although the building blocks operate at only 80 MHz. The circuit in simulation achieves 94 dB signal-to-noise ratio with a signal bandwidth of 5 MHz centered around an intermediate frequency of 80 MHz. Behavioral simulations of the complete sigma-delta modulator, including the most important non-idealities, as well as transistor-level simulations of the most critical building blocks are reported.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

F. Attivissimo, N. Giaquinto, M. Savino
CHEBYSHEV POLYNOMIALS AND DITHER TECHNIQUES FOR STATIC CHARACTERISTIC LINEARIZATION IN A/D CONVERTERS
The paper illustrates a new procedure, simple and very fast, to measure and correct the linearity error in A/D converters. The method is based on the Chebyshev polynomial synthesis of the static characteristic via frequency-domain analysis, and is especially effective for dithered converters.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Y. C. Jenq
FOURIER SPECTRUM OF D/A OUTPUTS WITH NON-UNIFORMLY SAMPLED DATA AND TIME-VARYING CLOCKS
In this paper, we investigate problems of D/A converters with non-uniformly sampled input data, and/or time-varying clock sources. The input digital data (which are stored in the memory to be read out and sent to a D/A converter) were obtained by sampling an analog waveform at non-uniform sampling intervals. (Quantization of data can also be considered as a form of non-uniform sampling.) Recently, there is available a new clocking system with a very fine time resolution and is capable of adjusting the clock period in a sample-to-sample basis. It is, therefore, interesting to consider the following question. "Given that the timing offset of each data sample is known, would it be beneficial to use this offset to adjust the read-out timing of the D/A converter?" To answer this question, we consider the following five different models: f₁(t) = Σ_n x(n T) g(t - n T), f₂(t) = Σ_n x(t_n) g(t - n T), f₃(t) = Σ_n x(n T) g(t - t_n), f₄(t) = Σ_n x(t_n) g(t - t_n), and f₅(t) = Σ_n x(t_n) g_n(t - t_n) where x(.) is the input analog signal, g(.) is the basic output pulse waveform of the D/A converter, T is the nominal sampling period and t_n is the n-th sampling time instance (for uniform sampling t_n = n T). Closed form expressions for the Fourier transform of the output signals for each model are derived. We also discuss some potential practical applications.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Salvatore Nuccio, Ciro Spataro
A SOTWARE TOOL TO ESTIMATE THE MEASUREMENT UNCERTAINTIES IN THE A/D CONVERSION BASED INSTRUMENTS
In the paper we present a numerical method, which permits to evaluate the measurement uncertainties of the A/D conversion based instruments overcoming the possible inapplicability of the pure theoretical approach prescribed in the ISO – "Guide to the Expression of Uncertainty in Measurement".
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Jerome J. Blair
CORRECTED RMS ERROR AND EFFECTIVE NUMBER OF BITS FOR SINEWAVE ADC TESTS
A new definition is proposed for the effective number of bits of an ADC. This definition removes the variation in the calculated effective bits when the amplitude and offset of the sinewave test signal is slightly varied. This variation is most pronounced when test signals with amplitudes of a small number of code bin widths are applied to very low noise ADC's. The effectiveness of the proposed definition is compared with that of other proposed definitions over a range of signal amplitudes and noise levels.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Tamás Zoltán Bilau, Tamás Megyeri, Attila Sárhegyi, János Márkus, István Kollár
FOUR PARAMETER FITTING OF SINE WAVE TESTING RESULTS: ITERATION AND CONVERGENCE
Small improvements to the iteration procedure of the IEEE Standard 1241-2001 are suggested, and extension of the standard MATLAB program implementing the sine wave test is discussed. The program is compatible with the LabView program already announced, and in other working modes offers extensions, too.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Marek Kurkowski, Pawel Ptak, Zygmunt Biernacki, Tadeusz Zloto
ACCURACY OF SIGNAL CONVERSION IN POWER MEASUREMENTS WITH LEM CONVERTERS
Among the phenomena significantly aggravating the quality of electric energy in the grid two are especially important: voltage fluctuations and deformations of voltage and current sinusoids.
The aim of the study described in the present paper was to improve the accuracy of signal converting in power measurements in non-linear receivers. The measurements of voltage and current were performed by means of a PC with measuring a card PCL-818L and with application software DasyLab 6.0 enabling the registration and converting of signals.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Marek Kurkowski, Zygmunt Biernacki, Tadeusz Zloto, Pawel Ptak
SIGNAL GENERATION AND ACQUISITION IN THE CORRELATION WTS
The paper deals with problems of signal analysis. Examples of system modelling by means of Dasylab package are discussed.
Measurements, analysis and visual presentation of selected signals were performed by means of measuring card PCL818 and Dasylab package. They are also described in the present paper [7].
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Tadeusz Zloto, Zygmunt Biernacki, Marek Kurkowski, Pawel Ptak
COMPUTER-AIDED SYSTEM FOR MEASURING TEMPERATURE OF ROTATING ELEMENTS
The paper includes a review of currently used devices for measuring temperature of rotating parts of machines. In the subsequent section it describes a computeraided measuring system developed by the authors. Using the optoelectronic measuring path, the system is employed for measuring temperature of cylinder block of an axial multipiston pump.
Besides, the application of DasyLab software package for the above mentioned measurements is presented.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Mustafa Keskin, Matthew E. Brown, Un-Ku Moonm, Gábor C. Temes
A VOLTAGE-MODE SWITCHED-CAPACITOR BANDPASS ΔΣ MODULATOR
A novel fourth-order voltage-mode switched-capacitor bandpass ΔΣ modulator, using direct-charge-transfer pseudo-N-path resonators, is described. This modulator is insensitive to component mismatches and finite opamp bandwidth, and is also less sensitive to finite opamp gain than previous bandpass ΔΣ data converters. It is therefore suitable for high-speed communications applications.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

F. Adamo, F. Attivissimo, N. Giaquinto
MATLAB TOOLBOXES FOR A/D CONVERTERS CHARACTERIZATION
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

J.J. Ocampo Hidalgo, A. Garcia Ortiz, L. D. Kabulepa, M. Glesner
ANALYSIS AND DESIGN OF A 4^th ORDER BANDPASS SIGMA DELTA MODULATOR FOR GSM COMMUNICATIONS STANDARD
This work addresses the design of a 4^th order bandpass sigma delta modulator (BPSDM) for IF AD converters suitable for second generation cellular standards such as GSM. The resonator architecture of a BPSDM can be derived from the transfer characteristic of a lowpass modulator by means of mathematical transformations. It can be observed that each transformation results in a different cascade of resonators (COR). Therefore different values of performance metrics like SNR, dynamic range, robustness against circuit non-idealities and SFDR can be expected. Behavioral simulations at the architectural level were carried out to find the COR that best meets the requirements imposed by the GSM communications standard and minimizes requirements of the sub-circuits used in the chosen architecture. A BPSDM was designed and sent to fabrication, using a 0.3 µm, double polysilicon, triple metal, N-well CMOS technology. Simulation results are showing that the proposed prototype reaches a SNR of 85 dB and a sampling rate of 80 MHz.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Milan Štork
MODIFIED Σ-Δ VOLTAGE TO FREQUENCY CONVERTER
Voltage to frequency converter (VFC) is an oscillator whose frequency is linearly proportional to control voltage. There are two common VFC architectures: the current steering multivibrator and the charge-balance VFC. For higher linearity, the charge-balancing method is preferred. The charge balanced VFC may be made in asynchronous or synchronous (clocked) forms. The synchronous charge balanced VFC or "sigma delta" (Σ-Δ) VFC is used when output pulses are synchronized to a clock. The charge balance VFC is more complex, more demanding in its supply voltage and current requirements, and more accurate. It is capable of 16 to 18 bit linearity.
Σ-Δ modulator can be used for synchronous VFC (SVFC). The synchronous behaviour is good in many applications, but the output of SVFC is not a pure tone (plus harmonics) like a conventional VFC, but it contains components harmonically related to the clock frequency. The SVFC produces a change in probability density of output pulses N and N+1 clock cycles after the previous output pulse.
In this paper, the modified SVFC (MSVFC) is described. This MSVFC works similarly as conventional SVFC but it has a pure tone on output (for constant input voltage). Therefore, it is possible to measure the period of MSVFC output (this does not work for SVFC).
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

R. Kochan, A. Sachenko, V. Kochan, N. Vasylkiv
UNIVERSAL SIGMA-DELTA ADC FOR INTELLIGENT DISTRIBUTED INSTRUMENTATION
In this papers the precision single-board, 8 channels, 24 bit sigma-delta ADC with on-line remote reprogramming mode is described. The results of experimental researches of the noise immunity of the developed ADC in real (industrial) measurement conditions are presented. The results of experimental researches of the prototype in the same measurement conditions are also considered.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

E. Garnier, A. Tetelin, Ph. Marchegay
CANCELLATION OF CHARGE INJECTION ERROR ON SWITCHED CURRENT DIVIDER CIRCUITS FOR ACCURATE D/A CONVERTERS
This paper proposes compensated methods to cancel the effects of charge injection error on switched-current Divider Circuits. Algorithmic structures of current dividers are presented and the final charge injection error is evaluated for each Algorithm. So, compensated methods to cancel this error are proposed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Daniel Belega
SYSTEM FOR TESTING ANALOG-TO-DIGITAL CONVERTERS
This paper presents a system named "ADC TEST" that estimates the static and dynamic parameters of an analog-to-digital converter according to the definitions given in IEEE Standard 1241. One shows the available output graphical pages with theirs information and facilities in a practical testing application.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Vadim Geurkov
A BUILT-IN SELF-CHECK METHOD FOR MULTI-CHANNEL MEASUREMENT SYSTEMS
Signature analysis techniques have become extremely popular in digital systems testing due to such advantages as simplicity, small amount of additional circuitry, and small degree of error masking. In this paper the signature analysis techniques are applied to mixed (analog-to-digital) systems testing. The general case of multi-channel measurement system is considered.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Stanislav Ďaďo, David Slepička
ADC TESTING BASED ON FREQUENCY ESTIMATION
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Ján Šaliga, Szabolc Csernok
C-LANGUAGE FUNCTION CLASS FOR SIGNAL PROCESSING AT ADC TESTING
The paper presents some ideas and results from the attempt to create a comprehensive suite of data processing, C-language functions that enables simplifying the development of new, user oriented software for testing analog to digital converters according the IEEE standards 1057, 1241 and DYNAD. The developed function class covers both dynamic and histogram based test methods. Nowadays, it is prepared in the form of instrument driver - function panel (*.fp) for the software development package Lab Windows⁄CVI by National Instruments. All functions were developed, debugged and tested in this environment.
The paper also contains some results from comparing the new developed function class used in a developed examples of end-user applications with test data processing Matlab software by Kollar and Markus.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

U. Frühauf, E.-G. Kranz, H. Leuterer
DEMONSTRATOR FOR RESOLUTION INCREASE AND AUTO-CORRECTION IN EMBEDDED MEASUREMENT SYSTEMS
For investigation and training of students in the field of high resolution measurement technology was built an embedded measurement system with 16 bit resolution and additional modules for self-diagnostics and autocorrection, including a monitoring measurement system for evaluation.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Matteo Parenti, Andrea Boni, Davide Vescovi
A 6-b 1Gsample/s SiGe BiCMOS A/D Converter
The paper describes the design of a 1GS/s 6-bit ADC in SiGe BiCMOS technology. Several techniques such as subranging, interpolation and averaging were implemented on the original flash architecture in order to achieve low power consumption without sacrificing linearity and dynamic performance.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Jan Fischer, Jan Vejdelek
REAL-TIME CORRECTION OF DC OFFSET OF LOW-COST AUDIO CODECS IN ACOUSTIC DIGITAL LOCK-IN AMPLIFIERS
In design of the DSP for acoustic applications it is appropriate to integrate a low-cost audio codec into their structure. Audio stereo codecs are able to achieve a high resolution of measurement on low frequencies of the input signal. But audio codecs are able to digitalize only signals of the acoustic origin, it means the signal without the DC part of frequency spectrum. In the majority of available DSP there are 2 independent AD converters and also 2 DA converters. But most of audio codecs create the DC offset during the conversion to the digital form, it means 0V voltage amplitude of input signal doesn’t correspond to 0_HEX in hexadecimal form of output digital word. The solution how to achieve the required parameters with these low-cost audio codecs is founded in this project.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

A.A. Platonov, K. Jędrzejewski, J. Jasnos
MATHEMATICAL AND COMPUTER MODELS IN MULTI-PASS ADC DESIGN AND OPTIMISATION
The paper presents a mathematically grounded approach to the analysis and optimisation of multi-pass analogue-to-digital converters (MADCs) with the algorithmic forming the estimates of converted samples. The approach enables a comprehensive analysis of the converter work using a virtual model of MADC built on the basis of its mathematical model. This model is based on the extended optimal identification algorithms adapted to the particularities of A/D conversion. The obtained sub-optimal algorithms take into account all main parameters of the internal auxiliary ADC and other analogue elements of MADC. The results of advanced simulations confirm a full agreement of theoretical and experimental evaluations, as well as efficiency of the proposed approach as a tool for MADC design support.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Zygmunt Biernacki, Tadeusz Zloto, Marek Kurkowski, Pawel Ptak
ANALYSIS OF ACCURACY AND MEASUREMENTS OF FLOWING MEDIUM PARAMETERS BY MEANS OF A WAVE THERMOANEMOMETER SYSTEM
The paper analyses the measurement accuracy of selected parameters, such as flow velocity and temperature, of a flowing medium, by means of the thermoanemometric method. The core of the method relies on the Wave Thermoanemometer System constructed by one of the authors. The sources of boundary error components are analysed within the signal conversion channels of the WTS. Errors are examined by means of relevant mathematical expressions representing signal conversion both in the velocity measuring channel and in temperature measuring channel. The algorithms have been developed for perfect and for real conditions. The theoretical considerations have been verified by laboratory tests performed by computerized equipment.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

J. Roztocil, D. Varga, M. Siroky
ASPECTS OF LOW DISTORTION SINE WAVE GENERATORS MEASUREMENT
This paper deals with testing of ultra-low distortion sine wave generators. Measurement of harmonic distortion based on lock-in amplifiers is described and practical results using fundamental-suppression method are presented.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Vasili K. Semenov
SUPERCONDUCTOR ADCS BASED ON PROCESSING OF SINGLE FLUX QUANTA
Superconductor ADCs exist and their performance is quickly approaching to those of the best semiconductor counterparts. Deep cooling could complicate a broad spreading of the still exotic superconductor technology. However, the technology is highly attractive for invention or at least numerical simulations of novel conversion schemes.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

T.H. Pearce
ADC DYNAMIC RANGE IMPROVEMENT FOR WIDEBAND HF RECEIVERS
The development of 14 bit monolithic Analogue to Digital Converters (ADC’s) capable of sampling at 80 MHz has revived interest in digitising the entire 3-30 MHz High Frequency (HF) radio spectrum for use in wideband HF receivers. This enables the ADC to be placed close to the antenna so removing the need for analogue mixing as well as offering a multi-channel reception capability, using multiple digital synthesisers and direct conversion I, Q mixing to baseband ...
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

John Pickering
DEVELOPING THE SIGMA-DELTA A-D FOR PRECISION DC&LF METROLOGY
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Alan J. Davies, Godi Fischer, Hans-Helge Albrecht, Jürgen Hess
IMPROVED NULL CANCELLATION IN A 6^th-ORDER Σ-Δ MODULATOR REALIZED WITH TWO 3^rd-ORDER SECTIONS
This paper presents an improved rnethod to digitally correct for statit, analog circuit imnperfections in a two-stage, 6^th order, cascaded (6-3) sigma-delta modulator. By adding a digital correction term to the output of die digital noise cancellation filter, the first stage parasitic quantization noise due to finite amplifier gain and C-Ratio mismatches can be completely removed. A 6-3 modulator implemented as a fully differential switched-capacitor circuit, designed for an OSR of 16, has heen fabricated in a 1.2 µm double-poly n-well CMOS process. Improvements have been made in the null cancellation leading to approximately a 10 dB increase in SNDR ovor a range of signal amplitudes from 12 µVolts to 500 mV. A peak SNDR/SFDR of 87/100 dB for a 1 MHz sample rate and 84/93 dB for a 2.5 MHz sample rate have heen achieved.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

János Márkus, Gábor C. Temes
AN EFFICIENT ΔΣ NOISE-SHAPING ARCHITECTURE FOR WIDEBAND APPLICATIONS
In this paper a new optimized multi-stage ΔΣ (Delta-Sigma) structure is proposed. The method combines the reduced-sample-rate architecture with the optimization of the zeros of the noise transfer function (NTF). To achieve this, the first stage of the decimation filter has to be modified as well. Applying this method one can avoid the SNR loss introduced by using the reduced-sample-rate second-stage. The SNR can actually increase for higher-order structures. Simulation results for a 2-0 MASH structure with an oversampling ratio of 4 are shown to verify the technique.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

X. Wang, U. Moon, G. C.Temes
DIGITAL CORRELATION TECHNIQUE FOR THE ESTIMATION AND CORRECTION OF DAC ERRORS IN MULTIBIT MASH ΔΣ ADCS
A fully digital algorithm is described for acquiring and correcting the errors of the feedback DAC used in a multibit ΔΣ MASH ADC. The method operates in the background and is highly accurate. It is particularly useful for wideband ADCs, where mismatch error shaping becomes ineffective. Combined with an improved digital adaptive compensation technique, which greatly reduces the raw quantization leakage in MASH architecture, it makes the design of fast and accurate ADCs using inaccurate components possible.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

D. Macii, P. Carbone, D. Petri
STABILITY ANALYSIS OF OSCILLATORS BASED ON A DELTA–SIGMA TOPOLOGY
The growing demand of mixed–signal integrated circuits encourages the research of Built-In Self-Test (BIST) techniques to achieve simpler and less expensive testing processes. High quality sinusoidal oscillators based on a Δ-Σ topology are an effective solution to perform the test of this kind of devices. Unfortunately, due to the in–loop 1–bit quantizer nonlinearity, several problems of stability have been observed. A stability analysis on the behavior of the oscillator based on a second order Δ-Σ modulator presented in [1] is described in this paper. In particular, it is shown that the oscillator is intrinsically unstable and its complete dynamics is very difficult to predict exactly. Finally, a possible stabilization strategy is proposed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

A. Moschitta, D. Petri
EFFECTS OF ADC INTEGRAL NON-LINEARITY ON DIGITAL TRANSMISSION
This paper investigates the effects of Integral Non-Linearity (INL) on the performances of both A/D converters and Digital Communication Systems, which exploit Direct Digital Modulation. The performances of both PCM and Sigma-Delta converters affected by INL are considered and compared. Then, the effects of INL upon the BER performances of an OFDM system are evaluated and modeled. The accuracy of the theoretical model is discussed with respect to the ADC resolution and INL levels. It is shown that a multibit Sigma-Delta converter, operating at a low oversampling ratio, may outperform PCM converters.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

R.K. Kamat, G.M. Naik
ANALOGUE TO DIGITAL CONVERTER WITH NON-LINEAR TRANSFER FUNCTION FOR THERMISTOR APPLICATIONS
There exists a disproportionate difference between dynamic range, resolution, and accuracy when the output of sensors having nonlinear characteristics like thermistors are digitized with the conventional linear ADCs. There are several methods to linearise the thermistor characteristics but at the expense of hardware, memory and time efficiency. This paper presents a new simple method of shaping the transfer function of a pulse width modulation ADC as per the thermistor characteristics. It is based on the principle of varying the amplitude of the reference voltage to reach the temperature equivalence of voltage being digitized.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

K. Ola Andersson, Niklas U. Andersson, Mark Vesterbacka, J. Jacob Wikner
COMBINING DACS FOR IMPROVED PERFORMANCE
This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Mark Vesterbacka, K. Ola Andersson, Niklas U. Andersson, J. Jacob Wikner
USING DIFFERENT WEIGHTS IN DACs
In this paper we discuss some properties of different codes with their respective sets of weights to be used in digital-to-analog converters (DACs). The thermometer (unratioed) code is widely used instead of a binary code in the most significant bits of a segmented DAC to reduce errors due to weight and timing mismatch. The binary and thermometer codes are two extremes, where the first offers a small digital hardware cost and the latter a large cost. We have investigated some of the properties of these codes and codes with properties in-between; such as linear, polynomial, and segmented codes. Some new ideas and results on using different sets of weights and how to generate them are presented. We present simulation results for some low-order polynomial codes.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

I. Vecera, R. Vrba
NOVEL PIPELINED SWITCHED-CURRENT A/D CONVERTER FOR SMART SENSORS
This paper describes pipelined switched-current A/D converter designed in 0.6 µm BiCMOS technology. Modified conventional-restoring algorithm, called redundant-sign-digit (RSD), was implemented what decreases the amount of high-precision components. Two modes of operation are possible. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Proposed A/D converter is suitable for conversion of the current with very low amplitude from analog into digital domain. Current mode enables operation down to 3 V thus is suitable for battery powered applications. The system integrates band-gap reference and independent supervisory circuit with 1% accuracy. Current consumption in sleep mode is less than 1 mA. A/D converter is prepared to meet 1452.2 specifications.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Alberto Die, Maurizio Valle
EVALUATION OF TIME RESOLUTION OF NMOS SAMPLING SWITCHES
Usually in CMOS line receivers and downconversion mixers, a key component is the NMOS sampling switch. When designing sampling switches, one has usually to trade off resolution against bandwidth and aperture time. In this perspective, we modeled the aperture time of the NMOS sampling switch for low swing voltage signals taking also into account the dependence of the threshold voltage on the body effect. Then we compared the aperture time behaviour using three submicron CMOS technologies (0.8, 0.5 and 0.25 μm minimum channel length respectively). The results indicate that an aperture time of about 100 ps is achievable with a CMOS 0.25 μm minimum channel length technology working at low supply voltage.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Reinhard Kindt, Richard Ižák
AN ANALOG APPROACH TO COMPENSATE FOR OpAmp OFFSET AND FINITE GAIN IN SC CIRCUITRY: A CASE STUDY OF A CYCLIC RSD ADC
Design of high-resolution Nyquist rate A/D converter necessitates the usage of advanced circuit techniques to compensate for arising analog errors. In switched capacitor ADC, besides the well know techniques such as bottom plate sampling, mismatch-independent and redundant (RSD: 1.5 bit/stage) conversion for the elimination of charge injection, capacitor mismatch, comparator and offset sensitivity, respectively, the most utilised circuit techniques are those for OpAmp’s offset and finite gain errors cancellation. An alternative technique for compensation of the errors due to finite gain and offset of Opamp in SC circuits is proposed. This novel method features a charge addition and is compared to so far used approaches based on voltage addition. The concept and the results of a 5 V CMOS implementation of cyclic RSD ADC with ratio-independent SC technique using this correction method are discussed.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

G.C. Cardarilli, A. Del Re, R. Lojacono, A. Nannarelli, M. Re
PERFORMANCE COMPARISON BETWEEN TRADITIONAL AND RNS-BASED ADC
Recently a new architecture for an analog to Residue Number System converter was proposed by the authors. In this paper a comparison of the performances, in terms of probability of LSB error due to internal noise, between a traditional ADC converter and this said analog to RNS converter is given.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Olli Vainio
ADAPTIVE SCHEME FOR OVERSAMPLED FRONT ENDS
A computationally efficient adaptive filtering scheme for oversampled A/D converters is discussed. The decimating digital filter is constructed as a combination of a sinc decimator and an adaptive predictor. A reduced-rank adaptive algorithm with two adaptive parameters is proposed for this purpose avoiding the complexity of the commonly used full-rank algorithms. The characteristics of the adaptive filter are considered, and a comparative example of data signal processing is shown.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Ivo Viščor, Josef Halámek
ACQUISITION SYSTEM WITH LOW JITTER
The high dynamic range system is often limited by the jitter. The sources of the jitter are the clock generator, the clock distribution and the ADC. Two different methods of the ADC jitter measurement are presented.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Carsten Wegener, Michael Peter Kennedy
TESTING ADCs FOR STATIC AND DYNAMIC NONLINEARITIES - KILLING TWO BIRDS WITH ONE STONE
Traditionally, static linearity and dynamic distortion tests are performed separately for ADCs. To this end, a low-frequency sinewave is histogrammed to measure static Integral Nonlinearity, and a high-frequency sine-wave is sampled for FFT processing to measure dynamic distortions and dynamic range.
We propose to use a model-based technique to extract both static and dynamic nonlinearities from a single data record of a sampled high-frequency sine-wave. This saves test time as the ADC converts fewer samples.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

J. Halámek, I. Višèor, M. Kasal, M. Villa, P. Cofrancesco
HARMONIC DISTORTION AND STATISTICAL ANALYSIS
The measurement of harmonics terms on two identical digital receivers with fast ADC (AD6644) is presented and statistically analyzed. The results are discussed according to the origin of harmonics and difference between spurious and harmonics.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

M. Comte, F. Azaïs, S. Bernard, Y. Bertrand, M. Renovell
ON THE EVALUATION OF ADC STATIC PARAMETERS THROUGH DYNAMIC TESTING
Full characterization of ADC requires both a histogram-based approach and a spectral analysis to determine respectively static and dynamic parameters. This paper investigates whether static performances can be extracted from spectral analysis, in order to develop a low-cost test procedure. Results show that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset and gain errors.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

Roland Holcer, Linus Michaeli
TESTING DNL AND INL OF ADC BY THE EXPONENTIAL SHAPED VOLTAGE
Testing of ADC’s differential nonlinearity DNL(k) by the histogram method requires the signal generator with extremely low distortion and high stability of the parameters. Besides this condition generator must be connected to the input of the ADC under test with high suppression of the interfering noise on ground line of instruments. The new type of testing signal has been proposed of the exponential form which could be generated by discharging of the capacitor across the resistance. The acquired digital samples from the output of ADC under test allow determining the best fitted exponential signal. The histogram from the registered samples and that for the best fitted exponential shape allows determining the differential nonlinearity DNL(k) for any code level k. Practical problems with generating the pure exponential shape are shown in this paper. The proposed method has been experimentally verified and was compared with the standardized methods.
4th Conference on Advanced A/D and D/A Conversion Techniques and their Applications and 7th Workshop on ADC Modelling and Testing, Prague, Czech Republic, 2002

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