IMEKO Event Proceedings

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Josef Vedral
EXPONENTIAL FIT TEST - THEORETICAL ANALYSIS AND PRACTICALLY IMPLEMENTATION
ADC testing by means of exponential signal is presented in the article. Time and frequency analysis of the signal is performed and Signal-to-Noise Ratio and Effective Number of Bits is calculated by means of Exponential Fit Test. The approach has been verified on 24-bit Flexible Resolution Digitizer PXI-5922 by National Instruments. Using exponential signal as the digitizer input, the SINAD = 106 dB corresponding to ENOB = 17,3 bits has been achieved. The difference of 1,5 bit was most probably caused by exponential signal frequency spectra decrease. Results comparable with classical sine-fit method indicate the possibility of consideration of the proposed method as an alternative digitizer test method. Achieved results prove the method applicability for dynamic testing of up to 16 bit digitizers, and method simplicity allows for embedded applications. The frequency spectra can be easily modified by changing the time constant of RC element.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Valeriy I. Didenko, Aleksandr V. Ivanov
DISTRIBUTION LAWS OF QUANTIZATION NOISE FOR SIGMA-DELTA MODULATOR
The very fast development of sigma-delta analog-to-digital converters is evidently. Therefore analytical methods of their description become more and more important. If the found equations are precise enough, they can be used for verification and validation of modelling and simulation. Analytical equations are also important from the viewpoint of education. As is known, the sigma-delta ADC consists of sigma-delta modulator (SDM) and digital filter. In this paper the quantization noise of modulator is investigated for different forms of input signal. The world known (classical) theory of quantization noise is not accurate nough. A new approach was supposed by the authors. The most important point of the approach is to use the discrete two-value distribution law at the modulator output. According to classical theory, for any forms of input signal the quantization noise at the output of the modulator has uniform distribution law. In accordance with new approach, the distribution law of quantization noise depends significantly on the form of input signal. The simulation results are found in agreement with new theory.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Carolina Luque A., Niclas Björsell
IMPROVED DYNAMIC RANGE FOR MULTI-TONE SIGNAL USING MODEL-BASED PRE-DISTORTION
Some test and measurement applications require higher dynamic range for multi-tone signals than a signal generator can generate. Moreover, for other applications it can be interesting to improve the performance of a “low cost” signal generator. The spectral purity of generated signals can be improved by using pre-distorted base-band signals. In this paper, a dynamic grey-box model is described. A pre-distorter is used in order to improve the dynamic range. The results, which are based on measurements, show an improved dynamic range for a three-tone signal of approximately 9 dB and an improved ACPR of 5 dB for a WCDMA signal.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Samer Medawar, Peter Händel, Niclas Björsell, Magnus Jansson
ADC CHARACTERIZATION BY DYNAMIC INTEGRAL NONLINEARITY
Wide band characterization of analog-digital converter integral nonlinearity (INL) based on parametric modeling and least-squares parameter fit is performed. In particular, the variations in the INL due to the frequency at the ADC stimuli are modeled. The INL is divided into two main entities describing the static and dynamic behavior of the ADC, respectively. The static component is modeled by a high code component (HCF) of piecewise linear segments centered around zero. A static low code (LCF) polynomial inherent to the INL data is added to the segments to describe the static part of the model. The INL dynamic part is modeled by an LCF polynomial. Method implementation is considered and is applied to 12-bit ADC data at 210 MSPS.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret
NONIDEALITIES STUDY OF A CONTINUOUS-TIME DELTA-SIGMA MODULATOR USING VHDL-AMS MODELLING
In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time Delta-Sigma modulator’s nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these non-ideal phenomena allows to estimate the limits of the modulator and hence to design more robust building-blocks.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Konrad Jędrzejewski
MODELLING AND SIMULATION ANALYSIS OF INTELLIGENT PIPELINE A/D CONVERTERS
The paper is devoted to the methods of analysis of a new class of “intelligent” pipeline A/D converters (IP ADC). The conversion scheme used in IP ADC is based on the original approach to optimisation of adaptive estimation systems. Its application to the pipeline A/D converters design enables to improve their characteristics but requires changes in their architecture and principles of conversion. The paper focuses on the modelling and analysis of dependence of IP ADC performance on the parameters of their analogue components and conversion algorithm. The models, methods and simulation tools, proposed and presented in the paper, enable efficient analysis of particularities of IP ADC work and definition of the most appropriate parameters of main components of the converter. They also enable assessment of the expected performance of IP ADC and its comparison with performance of known pipeline A/D converters. The results of selected simulation experiments are presented and discussed in the paper. The presented approach can be used at the initial stages of IP ADC design for effective choice of suitable architecture and parameters of the internal components of IP ADC.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Fabio Leccese
A SIMPLIFIED 3 –BITS DISCRETE PURE LINEAR ANALOG PREPROCESSING FOLDING ADC ARCHITECTURE
A simplified architecture of subranging pure linear folding ADC is proposed. The device is based on the folding idea to eliminate the DAC, the summing node and the amplifier, fundamental elements of the classical architecture, replacing them by means of an analogical signal preprocessing parallel structure named “channels”. The presented circuit in addition to the advantage of a reduction of total conversion time than a classical subranging ADC, so approaching ADC flashes, is very simple and easy to build. An accurate simulation of the single channels and of the whole structure validate the idea. A first discrete circuit it has been realized and tested.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Linus Michaeli, Ján Šaliga, Michal Sakmár, Ján Buša
SOME APPROACHES TO HISTOGRAM PROCESSING IN EXPONENTIAL STIMULUS ADC TEST
The paper presents a new approach to processing of the cumulative code histograms obtained at ADC histogram testing by exponential stimulus signal. The analytical base model requires calculation of logarithms that may not be convenient for implementation in some applications. The authors proposed two new approximation models of cumulative and code histograms derived from the analytical base model: recurrent model with rectangular rule and asymptotic model with the goal to simplify approximation process. The recurrent model is convenient for the implementation especially in digital signal processor because it uses only basic arithmetic operations. Estimation process using this model is also faster than using base one. The asymptotic model enables the fastest approximation of required parameters. The models were experimentally compared by simulation using Levenberg–Marquardt and Newton iteration algorithms.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Marián Chovanec, Linus Michaeli, Ján Šaliga
NOISE SHAPING STRUCTURES OF BAND PASS &SIGMA;&DELTA; ADC AND THEIR IMPACT ON METROLOGICAL PARAMETERS
The bandpass sigma delta analog-digital converters (BP ΣΔ ADC) represent the unconventional ADCs, which are mostly embedded into digital communication systems or direct conversion of the voltage vector into the digital complex number. The structure of the noise shaping feedback impacts dominantly S/N ratio. The various feedback structures of the BP ΣΔ ADC designed from their low-pass prototype will be presented in the paper. The impact of the proposed structures on the basic metrological parameters of the BPΣΔ ADC will be analyzed here.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

David Slepička
EASY ESTIMATION OF SPECTRAL PURITY OF TEST SIGNALS FOR ADC TESTING
ADC testing frequently confronts the problem of spectral purity of harmonic test signal. The majority of dynamic ADC test methods require test signal distortion at least 10 dB less than that of the tested ADC – the condition that cannot be practically fulfilled for testing up-to-date ADCs. More sophisticated approach to ADC testing applies the correction for test signal imperfections. In both cases test signal distortion has to be known – roughly in the first case and quite accurately in the second case. In this paper an easy method for the testing of signal spectral purity is proposed. Test signal passed by one of two simple analog filters is measured by a common ADC, whose nonlinearity is mathematically post-corrected. The results are compared with common approach applying notch filter and uncertainty analysis is performed.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Thomas E. Linnenbrink, William B. Boyer, Robert M. Graham, Nicholas G. Paulter, Jr., Steven J. Tilden
IEEE TC-10: UPDATE 2008
There is a world-wide need to standardize terms, test methods, and the computation of performance parameters for devices that generate, measure, and analyze waveforms. Users need to be able to unambiguously specify the device performance required for particular applications. Manufacturers need to be able to unambiguously state the performance of their devices (e.g., instruments, components, etc.). Metrology facilities need to perform calibrations with well-defined methods to produce reliable test results expressed in clear terms. Measurement instruments need to acquire data with well-defined methods and present it clearly. Technical Committee 10 (TC-10), the Waveform Generation, Measurement, and Analysis Committee of the IEEE Instrumentation and Measurement (I&M) Society, is tasked to develop standards to address these needs. TC-10 has developed IEEE standards to define terms and test methods for Digitizing Waveform Recorders (IEEE Std 1057-2007), Analog-to-Digital Converters (IEEE Std 1241-2000) and Transitions, Pulses, and Related Waveforms (IEEE Std 181-2003). It is currrently working on similar standards for Digital-to-Analog Converters (P1658) and Circuit Probes (P1696).
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Haifa FARES, Chiheb REBAI, Bertrand LE GAL, Dominique DALLET
OPTIMIZED DECIMATION STRUCTURE FOR COMPLEX BANDPASS &SIGMA;&DELTA; MODULATOR IN WIDEBAND RECEIVER
This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex bandpass ΔΣ modulator in wideband-standards receiver. The RF front-end has been based on a modified low-IF architecture and the full receiver dynamic range is converted into the digital domain. The approach proposed investigates a new decimation process and realizes new functionalities such as image rejection and frequency down conversion IF/DC by a complex mixing on &SIGMA;&DELTA; modulator bit stream. Two wide standards (IEEE 802.11a and 802.16) were chosen for design procedure illustration. The decimation structure was implemented on FPGA component using optimization techniques. Experimental results show the highspeed data rate and low-power consumption features of the proposed design.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Petr Struhovský, Ondřej Šubrt, Jiří Hospodka, Pravoslav Martinek
ADVANCED MODELING AND DESIGN EVALUATION PROCEDURE APPLIED TO PIPELINED A/D CONVERTER
This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC nonlinearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed in term of integral and differential non-linearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. The proposed procedure is demonstrated on a system design example of pipelined A/D converter. Simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment and finishing by an error source simulation and modeling of pipelined ADC structure, suitable for a generic process flow.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

A.A. Platonov, Ł.M. Małkiewicz, K. Jedrzejewski
FEB-BASED APPROACH TO THE MEASUREMENT OF EFFECTIVE RESOLUTION OF CYCLIC ADC
The goal of the paper is presentation of a new approach to the measurement of effective resolution (effective number of bits - ENOB) of the cyclic A/D converters (CADCs). The core idea of the approach is direct measurement of ENOB using, as a numerical measure, the number of true bits before the first erroneous bit (FEB) position. The position of FEB is determined as the first non-zero bit in the binary presentations of conversion errors. The definition of ENOB based on FEB is introduced and discussed. The particularities of the proposed method are analysed in simulation experiments. There are presented typical evolutions of FEB distributions in sequential cycles of conversion. Values of ENOB obtained using FEB-based method are compared with results obtained using the conventional approach to ENOB assessment. The comparison is performed on example of analysis of influence of DNL and INL errors of internal A/D converter on ENOB of CADC. The proposed method of the ENOB measurement gives more adequate information about the actual ADC resolution and weakens the influence of the form of testing signals on the results of the ENOB measurement.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Petr Cesak, Jan Fischer, Jaroslav Roztocil
ADC PERIPHERAL IN MICROCONTROLLERS
This paper presents an analog-to-digital converter (ADC) embedded as a peripheral in a microcontroller and influence of asynchronous digital input signals on results of ADC conversion. A schematic diagram of a successive approximation (SAR) ADC peripheral analog input circuit in a microcontroller was described and its model was designed. A practical measurement was performed using crosstalk measurement setup that consists of a MCB2100 Evaluation Board with a microcontroller LPC2129 and an external pulse generator triggered by the tested microcontroller. Measurement results proved that errors of DC measurement depend on a type of edge (rising or falling) of a digital input signal, a time when the edge occurs and an internal resistance of a DC source. The errors reached up to +2 LSB (resp. 2 LSB) depending on the edge type.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Vladimir Haasz, David Slepicka, Petr Suchanek
EXPERIMENTAL VERIFICATION OF DIFFERENT MODELS OF THE ADC TRANSFER FUNCTION
The performance of current devices is mostly limited by the analogue front-end and analogue-to-digital converter’s (ADC) imperfections. ADC performance is not, as commonly known, ideal. An important parameter is the nonlinearity, which (if it is known) can be corrected in the output data. The performance of three different approximations of ADC nonlinearity (common polynomials, Chebyshev polynomials and Fourier series), the approximations accuracy, and their coefficients’ sensitivity to noise is analyzed in the paper. Also an application of the approximated ADC nonlinearity for its correction is mentioned. The accuracy evaluation showed comparable results for small orders of all examined approximations. For higher number of estimated coefficients (few hundreds) the method using common polynomials fails while results using Chebyshev polynomials and Fourier series are similar. The noise sensitivity evaluation showed that an increase of maximum error is similar for all approximations in the case of the low number of coefficients. A rise of the number of coefficients escalates noise sensitivity in all examined cases. The nonlinearity correction was tested using the proposed approximations as well. This possibility was verified and in the presented case the improvement in the output signal spectrum achieved about 30 dB.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Anna Domańska
DITHER METHOD FOR LINEARIZATION OF STATIC CHARACTERISTIC OF A CLASS OF CONVERTERS
The characteristics of actual converters, including sensors, are – to smaller or larger extent – nonlinearity. With respect to the mathematical model describing the characteristics, they can be characteristics with smooth nonlinearity or nonlinearity with discontinuities. The author presented the problem of linearization of the characteristic of converter with nonlinearity with discontinuity that appears in the small value area, i.e. with insensitivity area. In general, this is not an easy task because of the type of nonlinearity and the local character of linearization. A method utilizing the technique of added noise (dither) is applicable in this purpose. It effectively removes nonlinearities in output signal, caused by the area, i.e. removes nonlinear distortions of the signal processed. Using dither makes it also possible to process signals with values wholly contained in the area, which would be impossible in a converter without applying the method. Side effects of applying the method are: amplitude reduction and phase shift of the processed signal, because of amplification error and phase error of the AV/LPF system, respectively. If we apply averaging it extends the time of processing.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

S. Grzelak, M. Zieliński, D. Chaberski
MEASURING DETERMINISTIC JITTER USING TIME INTERVAL MEASUREMENT SYSTEM
This paper describes the method of analysis of the measuring data obtained from low resolution and non-linear Time Interval Measurements System (TIMS) implemented in to FPGA device. Information about quantization and nonlinearity errors of TIMS warrants more precise analytical results during deterministic jitter investigation. The probability density function of the time-interval fluctuation can be very helpful during diagnosing of the jitter sources. As source of signal with deterministic jitter was used digital Delay Locked Loop (DLL) block, embedded in Virtex-E device. The TIMS with the suitable processing of the data allows observe and measure peak-to-peak value of deterministic jitter on the level of resolution of TIMS.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Giuseppe Cavone, Attilio Di Nisio, Nicola Giaquinto and Mario Savino
A MAXIMUM LIKELIHOOD ESTIMATOR FOR ADC AND DAC LINEARITY TESTING
The paper illustrates a method for simultaneous ADC and DAC linearity testing in a loop-back scheme. The main features of the method are: (i) it is statistically nearly optimal, being based on a maximum likelihood estimator; (ii) it does not require prior knowledge neither of the ADC nonlinearity, nor of the DAC nonlinearity – both are simultaneously measured relying only on a constant-variance noise. The performances of the method are studied both mathematically and via computer simulations. The method, because of its optimality and universality, appears to be also a good candidate for inclusion in technical standards relevant to ADC and DAC testing.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Germano Bianchi, Federico Perini, Claudio Bortolotti, Jader Monari, Stelio Montebugnoli, Mauro Roma
ADC BIT NUMBER AND INPUT POWER NEEDED, IN NEW RADIO-ASTRONOMICAL APPLICATIONS
For the most part, so far radio astronomy observations have been performed in protected frequency bands, reserved by ITU for scientific purposes. This means that, ideally, only the amplified equivalent system noise is present at the end of the receiver chain (i.e. the ADC input). So, typically, only a few bits are necessary to describe the signal (VLBI signals are digitised with only 2 bits), but today astronomers, in order to get more sensitivity and to boldly observe where no one has observed before, would like to study the radio sky even outside the protected bands. In these cases, a lot of man-made signals, coming both from terrestrial and space radio communication systems, are added to the very weak sky noise. For the first time, radio telescope designers must take in account the problem of the A/D converter dynamic range, since the increase of the total received power could lead the A/D to saturation. Here, a procedure to estimate the required number of bit (resolution and dynamic) and the input power level of an A/D converter, is described and applied to a new radio astronomical system which is under development at the Medicina radio observatory (Italy).
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Nejmeddine Jouida, Chiheb Rebai, Adel Ghazel, Dominique Dallet
THE IMAGE-REJECT CONTINUOUS-TIME QUADRATURE BANDPASS SIGMA-DELTA MODULATOR
This paper presents the design of an image-reject continuous-time (CT) quadrature bandpass (QBP) %Delta;%Sigma; modulator using a tailored signal-transfer-function (STF) design. The quadrature delta-sigma noise shaping with polyphase filter implementations and strategic IF placement effectively improve image rejection internally. The Fifth-order CT QBP %Delta;%Sigma; modulator planned for WiMAX and Bluetooth standards, illustrates clearly the totally elimination of image generation and the correctly signal process. This led to remove the baseband filter and PGA at the price of a very challenging ADC with merged-in cited functionalities. So, less analog components, low power consumption and high performance for the low-IF receiver.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

A. Moschitta, P. Carbone
TESTING DATA CONVERTERS WHEN SAMPLING IS INCOHERENT
Coherent sampling is a well known scheme for guaranteeing uniform distribution of sinewave phases. While such condition can be profitably exploited for testing Analog to Digital Converters (ADC) or Digital to Analog Converters (DAC), inaccuracies and non-idealities in both the signal generator and the sampling hardware make such condition rarely achievable. In this paper, the effect of deviations from the coherent sampling condition is analyzed, along with some effects on the related testing procedures.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Domenico Luca Carně, Domenico Grimaldi
SPECTRAL TEST OF DAC USING OVER SAMPLING AND LOW RESOLUTION ADC
In the paper a new testing method for spectral analysis of DACs is presented. The method requires low resolution high speed ADC to acquire the resulting signal obtained by adding to the output voltage of the DAC under test the periodic voltage with sawtooth shape. The zero crossing time sequence detected in the quantized signal is used to infer the value of the sawtooth voltage and, consequently, that of the output voltage of the DAC. Because the sampled signal is characterised by non-uniform sampling time, the spectral analysis is performed on the basis of a procedure pointed out to overcome the problem concerning the frequency ambiguities in the spectral analysis of non-uniform sampled signal. This procedure permits the reconstruction of the uniformly sampled spectrum by starting from the non-uniformly sampled one. The results of numerical test on 14-bit DAC by using 6 bit ADC were shown. Finally, the advantages of the method respect to another presented in literature, based on low resolution ADC and dithering, are discussed.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

S. Nuccio, C. Spataro
FIGURES OF MERIT FOR ANALOG-TO DIGITAL CONVERTERS: THE OPTIMAL SET FOR THE UNCERTAINTY EVALUATION
Choosing the right analog-to-digital converter for a stated measurement application and for a stated target uncertainty is not an easy task. In fact, each time the prospective purchaser browses among the manufacturer specifications, he finds different sets of parameters which qualify the product; moreover, the same figure of merit is often defined and measured in ambiguous way. One of the main reasons which has caused this situation is the coexistent of various Standards concerning the characterization of the analog-to-digital converters. The choice of the converter becomes more difficult taking into account that the potential buyer has to deal with the measurement uncertainty. Without question, the homogeneity of the figures of merit would facilitate the measurement evaluation. Target of the paper is the choice, among the large number of parameters proposed by the various Standards, of the optimal set of merit figures, which allows a correct uncertainty evaluation of a generic measurement performed by using an analog-to-digital converter. This want be a contribution toward the long awaited harmonization of the aforesaid Standards.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

Pier Andrea Traverso, Gaetano Pasini, Antonio Raffo, Domenico Mirri
THE DTCM CHARACTERIZATION APPROACH FOR THE QUALIFICATION OF DYNAMIC NON-LINEARITIES WITHIN A/D CHANNELS
The behaviour of both stand-alone ADCs and entire A/D acquisition channels under time-varying input excitations exhibits non-idealities which are peculiar to the dynamic operation and can not be described by the characteristics of the static response. In addition, even the common dynamic parameters suggested by the current standards usually fail to separately qualify the purely-dynamic non-linearities from all other perturbation effects on the system response. In this paper, the features of the Discrete-Time Convolution Model are discussed by pointing out the properties of the general approach from which it derives, with particular emphasis to the capability of separately describing all the system non-idealities on the basis of their nature. It will be shown how the DTCM characterization methodology and the set of related model parameters represent a suitable resource towards the separate qualification of dynamic non-linearities in A/D channels.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

M. Catelani, A. Zanobini, L. Ciani
WORD ERROR RATE MEASUREMENT IN ANALOG-TO-DIGITAL CONVERTERS: SOME STATISTICAL CONSIDERATIONS ABOUT IEEE STD 1241-2000, ANNEX A
The word error rate (WER) in an Analog to Digital Converter (ADC) is the probability of receiving an erroneous code for an input, after correction is made for gain, offset, and linearity errors, and a specified allowance is made for noise. Typical causes of word errors are metastability and timing jitter of comparators within the ADC. The aim of this paper is to give a contribution for a new draft of the IEEE Std 1241. Our attention is directed towards the word error rate estimation and to the Annex A of this standard. New statistical techniques which can better integrate what is sustained in the IEEE standard and have been proposed. In particular, Student and chi-square distributions have been introduced for a more accurate measurement of the word error rate in the case of n successive observations.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

AA. VV.
DEVELOPMENT OF INNOVATIVE METHODS FOR CHARACTERIZING, MODELING AND CORRECTING THE NON-IDEAL BEHAVIOR OF A/D AND D/A CONVERSION CHANNELS, IN ORDER TO CONTRIBUTE TOWARDS HARMONIZING AND UPGRADING INTERN
The research program aims at improving the performance of appliances based on Analog-to-Digital and Digital-to-Analog conversion (ranging from measuring instruments to on-chip ADC and DAC). This will be done by developing methods for the accurate measurement and correction of conversion errors (including, when applicable, errors caused by transducers and signal-conditioning blocks). Another aim of the research is to expand the scope of the theory of measurement uncertainty, including conversion errors in dynamic conditions. This will allow the manufacturers to qualify correctly the non-ideality of a conversion channel in the specifications, and the users to use correctly the given figures to compute the uncertainty introduced by the conversion. The research, developed for the parts of competence by the five coordinated Units, aims also at contributing in real terms towards the improvement and the harmonization of the existing standards, which currently present various discrepancy and obvious deficiencies with respect to the state of the art.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

E. Balestrieri, P. Daponte, S. Rapuano
PRELIMINARY REPORT ON ADC CHARACTERIZATION IN THE FREQUENCY DOMAIN IN THE INTERNATIONAL STANDARDS
The paper reports the latest results of the authors’ work within the project “Development of new methods for the characterization, modelling and correction of A/D and D/A conversion non-ideality, to contribute to the harmonization and the upgrade of the relative international standards”, co-funded by Italian Ministry of Education, University and Research. In particular, an experimental investigation for the harmonization of the measures of the ADC dynamic performance in the frequency domain, according to the standards in the field, is described. The comparison results show a good degree of similitude among the results provided using procedures and formulas from different standards of IEEE and IEC.
16th Symposium on Electrical Measurements and Instrumentation & 13th Workshop on ADC Modelling and Testing (IWADC), Florence, ITALY, 2008

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