IMEKO Event Proceedings

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Valeriy I. Didenko, Aleksander V. Ivanov, Aleksey V. Teplovodskiy
NEW APPROACH TO THEORY OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS
The main point of new approach to the theory of sigma-delta modulation is application of a discrete two-values distribution law for a quantization noise instead of a uniform distribution law accepted before. Due to the new approach, the variance (standard deviation in the square) of the quantization noise becomes dependent on input signal by parabolic function. The noise vs. frequency is found for different input signals taking into account all frequency range from zero to half of sampling frequency. Using dependence of standard deviation on input signal and frequency, different characteristics of sigma-delta modulation can be predicted, including SNR. Difference between analytical and simulation results for new theory can be driven to any small value.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Stephen Ralph, Ronan Farrell
DIRECT DIGITAL-TO-RF CONVERSION FOR MOBILE-PHONE BASESTATION APPLICATIONS USING BANDPASS SIGMA DELTA MODULATION
Sigma-delta modulator based digital-to-analog converters (DAC) have offered low-frequency designers a highly linear, high resolution data converter architecture that is highly amenable to integration with complex digital systems. Increasingly these data converters have been used to deliver all the power needed. In wireless applications, it is increasingly desirable to apply low-frequency sigma-delta techniques to RF signals and try to achieve similar benefits. In this paper we discuss the unique challenges that DACs in mobile phone basestations must satisfy and we present a flexible bandpass sigmadelta modulator architecture that can satisfy these criteria.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Domenico Luca Carně, Domenico Grimaldi
OVERSAMPLING METHOD FOR THE STATIC CHARACTERIZATION OF HIGH RESOLUTION DAC: A PROPOSAL FOR THEIEEE STANDARD P1658
The paper presents an improved implementation of a method pointed out for the static characterization of the new generation of high resolution Digital to Analogue Converters (DACs). Interesting aspect of this method is that the problem of the signal acquisition with high resolution is shifted to the simpler problem of the signal acquisition with high speed. In particular, the method is based on the comparison of the DAC output voltage with the analogue reference sinusoidal voltage and the detection of the Zero Crossing Sequence (ZCS) of the resulting signal by high speed ADC. The variation of the ZCS respect to that occurring in the sinusoidal reference signal is used to evaluate the DAC transfer characteristic. The improved implementation concerns the proper design characteristics that can be used as selecting criteria of the test equipment. In particular, the substitution of the ADC for the detection of the ZCS by the comparator device is investigated without affecting the accurate detection of the zero crossing. Moreover, the effects of the noise parameters affecting the generator feeding the reference analogue signal, as amplitude and phase noise, on the evaluation of the DAC static characteristic is analysed by considering test equipment using the comparator device and the high speed ADC, alternatively.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

F. Corręa Alegria, A. Cruz Serra
UNCERTAINTY ANALYSIS OF THE ADC HISTOGRAM TEST USING TRIANGULAR STIMULUS SIGNALS
This paper addresses the uncertainty of the estimates of ADC testing obtained with the Histogram Method when a triangular stimulus is used. Expressions are presented for the computation of the standard deviation of the transition voltages and code bin widths. These can be used for the Ramp Vernier Test which is a novel test method which will be included in the new version of the IEEE 1057 standard currently in balloting.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Vaclav Papez, Stanislava Papezova
HIGHLY PURE SINE-WAVE SIGNAL SOURCES FOR ADC TESTING
It is necessary to keep at the disposition test signals with a high spectral purity for series measuring e.g. in the area of metrology or electronics. Commercial signal generators do not satisfy higher requirements in this area. Our contribution describes chances of the improvement of their quality while using of suitable filters. There is described the construction of a special generator with a high spectral purity of a signal.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Dušan Agrež
DISTORTION ANALYSIS OF ANALOG-TO-DIGITAL CONVERTER BY IDFT AND LEAST-SQUARES FITTING ALGORITHM
This paper compares two basic procedures used in estimations of the significant components in the residual spectrum in the ADC dynamic testing. The properties of the weighted DFT interpolations for the frequency, amplitude, and phase estimations in order to reduce the leakage effect of the fundamental component in the investigation of the residual spectrum is described. The nonparametric interpolation algorithms retain all benefits of DFT approaches and improve the estimation accuracy as a function of a number of the signal cycles in the estimation interval. The comparison of the three-point estimation algorithms to the least-squares four-parameter sine-fit estimation described in the IEEE standard 1241 shows the estimation effectiveness.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Josef Vedral, Jan Neškudla
PSEUDORANDOM NOISE GENERATOR FOR ADC TESTING
This paper demonstrates two methods of noise signal generation for ADC testing. Digital pseudo-random number generator based on LFSR and combinations of LFRS are used. The objective of this exploration is to develop device for generation noise signal with uniformly distributed amplitudes. The signal should be used to measure parameters of AD converters using histogram test method.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Linus Michaeli, Michal Sakmár, Ján Šaliga
SOME ERRORS OF ANALOGUE SIGNAL SOURCES FOR ADC EXPONENTIAL STIMULUS HISTOGRAM TEST
This paper presents some typical errors of exponential stimulus generated by analog signal sources and their influence on errors of ADC testing by the histogram method. The analysed exponential signals are very close to linear signals such as triangular and sawtooth signals that can be very simply generated by active integrating circuit or passive integrating circuit with long time constant and/or the final voltage far beyond the ADC input range. The experimental measurements of some analogue generators on the market as well as passive and active generating circuit specially designed for the testing were performed. The sources of signal shape errors were investigated and capacitor was determined as the most critical component of generating circuit. The limitations of signal shape error were evaluated and related to the INL test error.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Ondrej Šubrt, Pravoslav Martinek, Carsten Wegener
A POWERFUL EXTENSION OF SERVO-LOOP METHOD FOR SIMULATION-BASED A/D CONVERTER TESTING
This paper deals with the virtual testing environment for analog-to-digital converters (ADCs) employing a novel and powerful extension of the Servo-Loop method. We build an improved version of the Servo-Loop targeted to full transistor-level circuit simulation of static integral and differential ADC non-linearity. In comparison with the conventional implementation, the Servo- Loop version proposed was enhanced by an effective search algorithm. The algorithm was implemented as a versatile Servo-Looper tool written in Verilog-A language which is suitable for direct co-operation with most of the analog and mixed-signal simulators used in industry. The prospective advantage of our approach is the fact that the implementation in Verilog-A creates an ideal opportunity to build a complex environment comprising the virtual testing engine as well as the DUT in the form of circuit-level ADC design or its behavioral model. At this point, the powerful capabilities of the proposed Servo-Looper tool were successfully confirmed by a large simulation set performed on the ADC behavioral model and the full custom ADC design example. The paper presents the most significant results of the ADC simulation procedure.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

David Slepicka
NOISE FLOOR IN ADC TESTING
The main goal of this paper is to introduce several definitions of noise floor and to show their application in ADC testing with regard to straightforward reading of some basic ADC parameters. The definitions and algorithms can be used for ADC standardization.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Vladimír Haasz, David Slepicka
POSTERIORI FREQUENCY SPECTRUM CORRECTION FOR TEST SIGNAL IMPERFECTIONS IN ADC TESTING AT 1MHZ PRACTICAL EXPERIENCE
In the last several years, many high-resolution and high-speed ADCs have appeared on the market. Since the signal purity of commercial generators particularly at MHz frequencies has not essentially increased in the same period, the problem of how to test ADCs has rose. This fact initiated the research of alternative methods based on either the application of special signals or posteriori correction of the measured sine-wave signal. The latter method concerning a simple correction in the frequency domain was analyzed, extended and practically applied. The application and the results of this extended method at the frequency of 1 MHz are presented in this paper.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Jiri Brossmann, Petr Cesak, Jaroslav Roztocil
ACCURACY OF ADC DYNAMIC PARAMETERS MEASUREMENT
Based on a model of a test signal generator, an accuracy estimator was designed and implemented. The proposed estimator uses computer simulations to obtain expected bias of dynamic parameters of an analog-to-digital converter (ADC). The usage of the method for estimation of ADC dynamic parameters measurement accuracy for the best sine-wave fit and the frequency domain analysis using the DFT will be presented in this paper
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Michael Soudan, Francesco Zanini, Ronan Farrell
METHODOLOGY FOR MINIMIZING TIMING MISMATCH IN TIME-INTERLEAVED ADCS
This paper describes a technique mitigating the impact of timing mismatches in timeinterleaved analog-to-digital converters (ADCs). The systems signal-to-noise and distortion ratio (SINAD) and spurious-free dynamic range (SFDR) are increased by controlling the selection order of the channels ADCs in combination with oversampling and consecutive filtering. The proposed method requires only knowledge of the relative level of timing mismatch between the channel ADCs though not the precise magnitude of the mismatch. The impact of timing mismatch on the SINAD and advanced selection ordering schemes are discussed. Moreover, simulation results are presented comparing the figures of merit of existing techniques.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

László Balogh, Balázs Fodor, Attila Sárhegyi, István Kollár
MAXIMUM LIKELIHOOD ESTIMATION OF ADC PARAMETERS FROM SINE WAVE TEST DATA
The sine wave test is maybe the most important method for characterizing ADC’s. By this, the acquisition device is excited with a sinusoidal signal, and a long series of output values is measured. With the help of these observations, the parameters of the DUT can be determined. The general method to do this is the Least Squares (LS). In this paper, we present a similar method using the Maximum Likelihood Estimation (MLE). It is more robust than the LS method, which has nice properties only under special conditions. This maximum likelihood problem is solvable only numerically. For this, a numerical method is presented, and simulation results are given. The main message of this paper is how to handle the problems of the estimation in the best way in order to extract possibly the full information from the measured data, and obtain a robust, effective algorithm.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Domenico Luca Carně, Domenico Grimaldi
STATE OF ART ON THE TESTS FOR ΣΔ ADC
The paper deals with the state of art on the tests for both ΣΔ modulators and ΣΔ Analog to Digital Converters (ADCs). Particular aspects are highlighted concerning the tests for the innovative architectures based on the Band Pass ΣΔ ADC. The analysis of the tests is carried out in conjunction with the discussion about the applicability of the procedures included into the IEEE Standard 1241. Therefore, three fundamental groups of tests are defined: (i) tests according to the IEEE Standard 1241, (ii) tests included into the IEEE Standard 1241 but executed in a different way from the Standard, and (iii) tests pointed out to evaluate the specific characteristics of the ΣΔ modulator not included into the IEEE Standard 1241.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Attilio Di Nisio, Laura Fabbiano, Nicola Giaquinto, Mario Savino
STATISTICAL PROPERTIES OF AN ML ESTIMATOR FOR STATIC ADC TESTING
A maximum likelihood estimator is derived for the problem of measuring the code transition levels of an ADC. The proposed method is intended to characterize the ADC in the static regime, using only constant test signals, except for a small amount of additive noise. The measurement data are employed in a nearly optimal manner, due to the statistical properties of the maximum likelihood estimator, which are thoroughly examined. The reported analysis allows the design of the test under a given uncertainty constraint.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

N. Björsell, M. Isaksson, P. Händel, D. Rönnow
KAUTZ-VOLTERRA MODELLING OF AN ANALOGUE-TO-DIGITAL CONVERTER USING A STEPPED THREE-TONE EXCITATION
In many test and measurement applications, the analogue-to-digital converter (ADC) is the limiting component. Using post-correction methods can improve the performance of the component as well as the over all measurement system. In this paper an ADC is characterised by a Kautz-Volterra (KV) model, which utilises a model-based post-correction of the ADC with general properties and a reasonable number of parameters. Results that are based on measurements on a high-speed 12-bit ADC, shows good results for a third order model.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Cristian Zet, Catalin Damian, Cristian Fosalau
NEW TYPE ADC USING PWM INTERMEDIARY CONVERSION
The paper presents a new ADC type that uses an intermediary conversion in PWM signal. The signal is compared with a triangular wave. The pulse width at comparator’s output results proportional with the input voltage. Using a simple counter or a frequency-meter like circuit, it is converted into digital words. This is not a very fast converter (up to 10kS/s) but it is easy to build and it asks reduced costs to expand to multiple simultaneous sampling. This design is aimed for FPGAs, having outside it just a comparator per channel. Hardware signal processing is available immediately in the FPGA. Resolution and accuracy can go as far as 12, 14 or 16 bits. The converter presented in the following is 12 bits resolution and measure voltages from -2 V to 2 V. Static errors are also presented.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret
VHDL-AMS BEHAVIOURAL MODELLING OF HIGH-SPEED CONTINUOUS-TIME DELTA-SIGMA MODULATOR
An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF frontend receivers.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Roberto Lojacono, Arianna Mencattini, Marcello Salmeri, Silvia Sangiovanni
REFERENCE FOLDING SUBRANGING CALIPER ADC
The paper presents a reduced ADC architecture obtained by introducing the subranging technique into the scheme of a caliper AD converter. This last converter was already proposed as an application of a theory which describes the comparison between scales having the steps prime each other. This converter architecture drastically reduces the number of the required resistors for a full flash realization. The introduction of the subranging technique into the caliper ADC here presented reduces also the number of the required comparators. The result is a very compact architecture. The paper describes a first intention architecture based on ideal components. An example of SPICE simulation is given.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Petr Suchanek, Vladimir Haasz
APPROACHES TO THE ADC TRANSFER FUNCTION MODELLING
It is necessary to keep at the disposition test signals with a high spectral purity for series measuring e.g. in the area of metrology or electronics. Commercial signal generators do not satisfy higher requirements in this area. Our contribution describes chances of the improvement of their quality while using of suitable filters. There is described the construction of a special generator with a high spectral purity of a signal.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Nejmeddine Jouida, Chiheb Rebai, Adel Ghazel, Dominique Dallet
VHDL-AMS MODELLING OF CONTINUOUS-TIME COMPLEX BANDPASS DELTA SIGMA MODULATOR
Continuous-Time delta sigma modulators (CT ΔΣM), by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. In this work, we present a top level behavioral approach of modeling CT complex Bandpass (CBP) ΔΣM using VHDL-AMS language. The CT ΔΣ model can be used within the analog IC design environment. Fifth-order CT CBP ΔΣM which is tailor made for Bluetooth and WiFi Low-IF receiver demonstrates clearly the modeling technique.
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

Aldo Baccigalupi, Mauro D’Arco
AN EXPERIMENTAL STUDY AIMED AT ANALYSING HORIZONTAL QUANTIZATION AND TIME-BASE JITTER EFFECTS IN WAVEFORMS GENERATED BY MEANS OF DACS
This work analyzes the imperfections that characterize waveforms generated by means of DACs. The attention is mainly paid to horizontal quantization, which is due to the discrete nature of the waveform to be played. Also the effects of time-base jitter, which occur in DAC functioning, are investigated when combined to horizontal quantization. Further remarks are related to other minor effects such as those caused by vertical quantization, which is due to the limited resolution of any DAC
12th Workshop on ADC Modeling and Testing, Iasi, ROMANIA, 2007

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